We are sharing a specialised part-time consulting opportunity for experienced digital chip design and verification professionals with strong backgrounds in RTL development, SystemVerilog, ASIC workflows, verification infrastructure, and frontier silicon engineering workflows.

This role supports current and upcoming remote consulting opportunities focused on structured silicon design review, RTL development, design verification, simulation debugging, technical documentation, and high-quality project execution. Selected professionals will apply their digital design or verification expertise to review realistic chip-design scenarios, evaluate technical outputs, prepare structured written deliverables, and support accurate, evidence-based silicon engineering workflows.

Key Responsibilities

Professionals in this role may contribute to:

RTL Design & Digital Architecture Review

• Review digital design scenarios involving RTL modules, FSMs, datapaths, pipelines, FIFOs, arbiters, clock and reset domains, bus protocols, and SoC-level design components
• Evaluate RTL implementations against design requirements, architectural intent, timing considerations, synthesis expectations, and technical constraints
• Support structured review of Verilog and SystemVerilog code, design documentation, simulation outputs, waveform traces, and debug materials
• Identify logic issues, integration gaps, unclear tradeoffs, and expected RTL design outcomes

ASIC Flow, Debug & Implementation Support

• Review ASIC design workflow materials involving lint, synthesis, timing analysis, CDC, DFT-aware design, waveform debug, and simulation logs
• Evaluate design outputs against source documentation, tool reports, design constraints, and implementation expectations
• Support structured review of materials connected to common EDA tools for simulation, waveform viewing, linting, CDC analysis, synthesis, and timing review
• Prepare clear written explanations for design decisions, debug findings, and technical tradeoffs based on source materials and verifiable criteria

Design Verification & Coverage Review

• Review verification scenarios involving SystemVerilog, UVM, reusable verification components, testbench infrastructure, constrained-random testing, SVA assertions, and functional coverage
• Evaluate verification plans, test cases, scoreboards, reference models, coverage reports, regression results, and debug reports against defined verification goals
• Support structured review of coverage closure workflows, regression flows, formal verification materials, and verification IP
• Maintain accuracy, consistency, and professional judgment across submitted work

Ideal Profile

Strong candidates may have:

• 3–10 years of experience in RTL design, digital design, ASIC design, design verification, SoC verification, or related silicon engineering roles
• Strong proficiency in Verilog, SystemVerilog, RTL development, UVM, or verification infrastructure depending on track
• Solid understanding of digital design fundamentals such as FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols, and timing considerations
• Experience with ASIC workflows such as lint, synthesis, timing analysis, CDC, DFT-aware design, simulation, waveform debug, formal verification, coverage analysis, or regression management
• Familiarity with LLM-based tools used to support chip design, RTL development, debug, documentation, verification, test generation, or coverage review
• Strong written communication skills and ability to explain technical reasoning, design tradeoffs, and debug conclusions clearly

Educational Background

• A degree or professional background in electrical engineering, computer engineering, computer science, semiconductor engineering, digital design, or a related technical field is helpful
• Equivalent practical experience in RTL design, ASIC design, design verification, silicon validation, or chip development workflows is also highly relevant

Nice to Have

• Experience with AMBA protocols such as AXI, AHB, or APB
• Background in CPU, GPU, ML accelerator, networking, memory subsystem, PCIe, high-speed IO, SoC interconnect, or low-power design
• Exposure to formal verification, SV/UVM-based verification, reusable verification IP, scoreboards, reference models, or coverage-driven regression flows
• Experience preparing or reviewing design specs, verification plans, RTL documentation, debug reports, waveform analyses, coverage reports, or technical implementation notes
• Strong attention to detail in complex, simulation-heavy, and highly technical silicon engineering environments

Why This Opportunity

• Apply digital silicon design and verification expertise to structured remote project work
• Contribute to high-quality RTL review, verification assessment, debug analysis, and silicon workflow documentation
• Work on focused assignments aligned with your chip-design background
• Use your engineering judgment in a rigorous, detail-oriented technical environment
• Remote structure with competitive hourly compensation

Contract Details

• Independent contractor role
• Fully remote for professionals based in the United States or Canada
• High-availability commitment preferred, with full-time availability of approximately 40 hours per week depending on project needs
• Target engagement of approximately 3+ months depending on scope and performance
• Competitive rates between $115–$200 per hour depending on expertise
• Weekly payments via Stripe or Wise
• Projects may be extended, shortened, or adjusted depending on scope and performance
• Work will not involve access to confidential or proprietary information from any employer, client, or institution

About the Platform

This opportunity is available through 24-MAG LLC. We connect experienced professionals with remote consulting opportunities across technical, evaluation, and project-based workstreams.

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